{"product_id":"9789355850119","title":"Test and Testability for JNTU-H 18 Course (IV - II - ECE - EC822PE) - Professional Elective – VI (Decode)","description":"\u003cp\u003eUNIT - I Need for testing, the problems in digital Design testing, the problems in Analog Design testing, the problems in mixed analog\/digital design testing, design for test, printed-circuit board (PCB) testing, software testing, Fault in Digital Circuits : General Introduction, Controllability and Observability, Fault Models, stuck at faults, bridging faults, CMOS technology considerations, intermittent faults. (Chapter - 1) UNIT - II General Introduction, to test pattern genration, Test Pattern generation for combinational logic circuits, Manual test pattern generation, automatic test pattern generation, boolen difference method, Roth’s Dalgoritham, Developments following Roth’s D-algoritham, Pseudorandom test pattern generation. (Chapter - 2) UNIT- III Pseudorandorn test pattern generators, Design of test pattern generator using Linear feedback shift registers (LFSRs) and cellular automata(CAs). (Chapter - 3) UNIT- IV Design for Testability for combinational circuits : Basic Concepts of testability, controllability and observability, the Reed Muller’s expansion techniques, use of control logic and syndrome testable designs. (Chapter - 4) UNIT- V Making sequential circuits testable, testability insertion, full scan DFT technique-Full scan insertion, flipflop structures, Full scan design and test, scan architectures-full scan design, shadow register DFT, partial scan methods, multiple scan design, other scan designs.  (Chapter - 5)\u003c\/p\u003e","brand":"Technical Publications","offers":[{"title":"Default Title","offer_id":46993118298404,"sku":"9789355850119","price":120.0,"currency_code":"INR","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0671\/3661\/8788\/files\/9789355850119_1.jpg?v=1694686794","url":"https:\/\/bookstation.in\/products\/9789355850119","provider":"BookStation","version":"1.0","type":"link"}